1. Field of the Invention
The present invention relates to an image sensor and an electronic information device, particularly to an improvement in quality of locally bright images such as sunlight and the like. The present invention can be applied to a pixel read circuit such as of a CMOS image sensor used in an electronic image capturing device such as a video camera, a digital camera and the like.
2. Description of the Related Art
FIG. 8 is a diagram describing a conventional image sensor. This diagram shows one pixel in an image sensor and a circuit holding a signal value read from the pixel. FIG. 9 is a timing chart describing the operation of a conventional image sensor.
A pixel 200 constituting the conventional image sensor 20, as shown in FIG. 8, for example, comprises a photo diode PD which is a photoelectric conversion element for converting light into electrons, a reset transistor M1 for resetting the cathode potential thereof to a reset voltage, a read transistor M2 for amplifying and reading the photoelectric conversion signal generated at the photo diode PD and reading as a pixel voltage, and a selecting transistor M3 for selecting the pixel.
In the image sensor, a plurality of such pixels 200 is arranged in a matrix, and a read line 202 is located for each pixel column. All pixels of one pixel column are connected to a read line 202, and each read line 202 is connected to one constant-current source 203.
Moreover, a sample and hold circuit 210 is connected to each read line 202, and the sample and hold circuit 210 holds a pixel voltage read to the read line 202 which corresponds to the cathode potential of the photo diode.
A reset noise is superimposed to the cathode potential when resetting. This reset noise is different for every pixel since it depends on the dispersion in transistor characteristic and dispersion in parasitic capacitance in the pixel. Herein, in order to remove this reset noise, a correlated double sampling circuit is used for the sample and hold circuit 210. This correlated double sampling circuit holds a reset voltage which is a reference voltage of each pixel and a pixel voltage generated by a photoelectric conversion in each pixel, respectively, and detects a pixel signal of each pixel based on a voltage difference of these voltages.
Next, the operation is described.
First, when the pixel selection signal (SEL) is at an H level, the selecting transistor M3 is turned on and a predetermined pixel 200 is selected.
Then, a first reset operation is performed in a reset time period T1. That is, by the reset (RST) signal being at an H level and the reset transistor M1 being turned on, the gate of the read transistor M2 is charged by a reset voltage, the read transistor M2 is turned on, and the read line 202 becomes a reset potential. To be exact, although the reset potential (i.e., gate potential of a read transistor while the reset transistor is turned on) is a potential lower than the source potential VD by the amount of threshold voltage of the reset transistor M1, in the operational description of the pixel, the reset potential is also referred to as the VD voltage at portions where there is no particular distinction needed between them.
In the integral time period T2 thereafter, RST signal is at an L level, and the reset transistor is turned off. Thus, the potential of the gate 201 of the read transistor M2 gradually decreases due to the charge generated at the photo diode PD, and the pixel voltage read to the read line 202 also gradually decreases.
The correlated double sampling circuit 210 samples and holds the pixel voltage Vs read to the read line 202 as a signal voltage just before the end of the integral time period T2.
After the second reset operation is performed in time period T3, the correlated double sampling circuit 210 samples and holds the pixel voltage VD′ read to the read line 202 as a reset voltage, within the reset level read time period T4 which is shorter than the integral time period T2.
The sample and hold circuit outputs the voltage difference between the signal voltage Vs which was sampled and held at the integral time period T2 after the first reset operation and the reset voltage VD′ which was sampled and held within the short time period T4 after the second reset operation, as the pixel signal which is a photo-detection signal detected at the pixel.
In this way, by outputting the difference between the two sample and hold voltages, a reset noise is removed from the pixel signal read from the pixel.
However, when an area with a luminance which is extremely high compared with the surrounding images such as sunlight and the like locally exists in the captured image, with the pixel which corresponds thereto, the photoelectric conversion current generated by the photo diode becomes extremely large. Therefore, as shown in FIG. 9(b), in the reset noise read time period T4 after the second reset operation, the cathode potential thereof rapidly decreases.
As a result, the voltage difference between the two sample and hold voltages becomes very small. That is, originally, at the area with a high luminance such as sunlight and the like, the pixel signal level to be detected is expected to be at a maximum level. However, since the reset noise read in the reset noise read time period becomes too large, the pixel signal level cannot be obtained as expected. Thus, the obtained output image is an image with an extremely low sunlight luminance. In an extreme case, as shown in FIG. 12(a), the sun becomes a black image Im1.
In the conventional image sensor, a method for improving the quality of the image with a local high luminance is studied. For example, Reference 1 discloses an example.
FIG. 10 is a diagram describing an image sensor disclosed in this reference. In FIG. 10, similar reference numerals refer to similar parts of FIG. 8.
The image sensor 20a comprises a control circuit 204 inserted between the read line 202 and the correlated double sampling circuit 210 in the conventional image sensor 20 shown in FIG. 8. The image sensor 20a controls such that the potential supplied from the read line 202 to the correlated double sample and hold circuit 210 does not become lower than the predetermined threshold value Vth, in the reset noise read time period T4.
The control circuit 204 includes a two-input OR circuit 207 for inputting an enabling (EN) signal and a signal from the read line 202, an inverter INV for inverting the output of the OR circuit 207, a transmission transistor M40 connected between the read line 202 and the correlated double sampling circuit 210 wherein the output of the OR circuit 207 is input to the gate, and a pull-up transistor M50 for fixing the input of the correlated double sampling circuit 210 at the VD voltage wherein the gate is connected to the output of the inverter INV.
In this image sensor 20a, during signal reading (time period T2), the EN signal input to the OR circuit 207 in the control circuit 204 is fixed at an H level. At this time, since the output 205 of the OR circuit 207 is always at an H level, the transmission transistor M40 connected between the read line 202 and the output signal 206 of the control circuit 204 is in an ON state.
At this time, since the input signal 205 of the inverter INV in the control circuit 204 is at an H level, the output signal of this inverter INV is at a L level. Thus, the gate of the pull-up transistor M50 for the output signal 206 of the control circuit 204 is at a L level, and the pull-up transistor M50 is in an OFF state.
Therefore, the voltage level of the read line 202 is transmitted to the correlated double sampling circuit 210 through the control circuit 204.
Next, during reset level reading (time period T4), in the image sensor 20a, the EN signal input to the OR circuit 207 in the control circuit 204 is fixed at a L level. When the image includes an image with a local high luminance such as the sun and the bulb, the voltage of the read line 202 which is another input signal of the OR circuit may become lower than the threshold value of the OR circuit. At this time, since the output 205 of the OR circuit is at a L level, the transmission transistor M40 connected between the read line 202 and the output signal 206 of the control circuit 204 is in an OFF state.
At this time, since the input signal 205 of the inverter INV in the control circuit 204 is at a L level, the output signal of the inverter INV is at an H level. The gate of the pull-up transistor M50 for the output signal 206 of the control circuit 204 is at an H level, and the pull-up transistor M50 is in an ON state. Therefore, the output signal 206 of the control circuit 204 is held at the VD voltage.
FIG. 11 is a timing diagram describing a specific circuit operation when the image sensor shown in FIG. 10 is receiving a strong light (during high luminance). FIG. 11 shows a pixel signal read operation during high luminance and a reset signal read operation during high luminance. Herein, a state in which the pixel 200 is selected is shown, and the SEL signal selecting the pixel 200 is at an H level.
The pixel signal read operation during high luminance is described.
At the first reset time period T1, the RST signal is at an H level. With the reset transistor M1 shown in FIG. 10 being turned on, the gate 201 of the read transistor M2 is at the VD voltage. Since the SEL signal is at an H level, the selecting transistor M3 is in an ON state. Therefore, the level of the read line 202 is at the VD voltage.
At this time, since the EN signal shown in FIG. 11 is at an H level, the OR circuit output 205 in the control circuit 204 is at an H level, and the transmission transistor M40 is in an ON state. Thus, the VD voltage of the read line 202 is transmitted to the output 206 of the control circuit 204. Therefore, as shown in FIG. 11, the output 206 of the control circuit 204 is at the VD voltage.
Next, in the integral time period T2, since the RST signal is at a L level, the reset transistor M1 is turned off, and as a result, due to the current generated by the photo diode and the reset noise, the voltage at the gate 201 of the read transistor M2 is decreased. During high luminance, the gate 201 of the read transistor M2 is at or lower than the threshold voltage of the read transistor M2, and the read transistor M2 is turned off.
At this time, since there is no more current supplied from the pixel 200 to the constant-current source 203, the read line 202 is at a minimum voltage, and the output 206 of the control circuit 204 is also at a minimum voltage. This minimum potential is held at the correlated double sample and hold circuit 210 as a signal potential in the integral time period T2.
The reset operation during high luminance is described.
At the second reset time period T3, the RST signal is again at an H level. Similar to the first reset time period T1, the gate 201 of the read transistor M2 is at the VD voltage.
Next, when the RST signal is at L a level, the reset read time period T4 starts. In this time period, due to the influence of the reset noise and the luminance signal, i.e., the current generated by the photo diode shown in FIG. 10, the voltage at the gate 201 of the read transistor M2 in the pixel 200 shown in FIG. 10 decreases. During high luminance, similar to the integral time period T2, the gate 201 of the read transistor M2 is at or lower than the threshold value of the read transistor M2, and the read transistor M2 is turned off. Therefore, the read line 202 is lowered to the minimum voltage.
Then, during the time for detecting the reset signal, the EN signal input to the control circuit 204 is at a L level. Therefore, when the voltage of the read line 202 is at or lower than the threshold voltage Vth of the OR circuit in the control circuit 204, since the other input signal EN is at L level, the OR circuit output 205 in the control circuit 204 is at L level. Since this OR circuit output 205 is a gate signal of the transmission transistor M40, the transmission transistor M40 is turned off. The output of the inverter INV which has the OR circuit output 205 as the input is at H level. By the pull-up transistor M50 being turned on, the output signal 206 of the control circuit 204 is at the VD voltage.
This VD voltage is held by the correlated double sampling circuit 210 which is the step after the control circuit 204, before the EN signal is at H level, within the reset read time period T4.
In this way, the difference between the signal voltage which is the output signal 206 generated in time period T2 (minimum voltage) and the reset voltage which is the output signal 206 generated in time period T4 (VD voltage) is detected at the correlated double sampling circuit 210, and the pixel signal during high luminance is output.    Reference 1: Japanese Laid-Open Publication No. 2004-112740